/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /** * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the * board. * * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf * * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM * * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; /plugin/; #include #include #include #include "k3-pinctrl.h" #include "k3-serdes.h" &{/} { aliases { ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; }; }; &main_cpsw0 { status = "okay"; }; &main_cpsw0_port5 { phy-handle = <&cpsw9g_phy1>; phy-mode = "qsgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>; phy-names = "mac", "serdes"; status = "okay"; }; &main_cpsw0_port6 { phy-handle = <&cpsw9g_phy2>; phy-mode = "qsgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>; phy-names = "mac", "serdes"; status = "okay"; }; &main_cpsw0_port7 { phy-handle = <&cpsw9g_phy0>; phy-mode = "qsgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; phy-names = "mac", "serdes"; status = "okay"; }; &main_cpsw0_port8 { phy-handle = <&cpsw9g_phy3>; phy-mode = "qsgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>; phy-names = "mac", "serdes"; status = "okay"; }; &main_cpsw0_mdio { pinctrl-names = "default"; pinctrl-0 = <&mdio0_default_pins>; bus_freq = <1000000>; reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; reset-post-delay-us = <120000>; #address-cells = <1>; #size-cells = <0>; status = "okay"; cpsw9g_phy0: ethernet-phy@16 { reg = <16>; }; cpsw9g_phy1: ethernet-phy@17 { reg = <17>; }; cpsw9g_phy2: ethernet-phy@18 { reg = <18>; }; cpsw9g_phy3: ethernet-phy@19 { reg = <19>; }; }; &exp2 { /* Power-up ENET1 EXPANDER PHY. */ qsgmii-line-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_HIGH>; output-low; }; }; &main_pmx0 { mdio0_default_pins: mdio0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ >; }; }; &serdes_ln_ctrl { idle-states = , , , , , , , , , , , ; }; &serdes_wiz2 { status = "okay"; }; &serdes2 { #address-cells = <1>; #size-cells = <0>; status = "okay"; serdes2_qsgmii_link: phy@0 { reg = <2>; cdns,num-lanes = <1>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz2 3>; }; };