// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree For AC5. * * Copyright (C) 2021 Marvell * Copyright (C) 2022 Allied Telesis Labs */ #include #include / { model = "Marvell AC5 SoC"; compatible = "marvell,ac5"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; }; }; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2>; }; l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; pmu { compatible = "arm,cortex-a55-pmu"; interrupts = ; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; bus@7f000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; /* 16M internal register @ 0x7f00_0000 */ ranges = <0x0 0x0 0x7f000000 0x1000000>; dma-coherent; uart0: serial@12000 { compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; interrupts = ; reg-io-width = <1>; clocks = <&cnm_clock>; status = "okay"; }; uart1: serial@12100 { compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; interrupts = ; reg-io-width = <1>; clocks = <&cnm_clock>; status = "disabled"; }; uart2: serial@12200 { compatible = "snps,dw-apb-uart"; reg = <0x12200 0x100>; reg-shift = <2>; interrupts = ; reg-io-width = <1>; clocks = <&cnm_clock>; status = "disabled"; }; uart3: serial@12300 { compatible = "snps,dw-apb-uart"; reg = <0x12300 0x100>; reg-shift = <2>; interrupts = ; reg-io-width = <1>; clocks = <&cnm_clock>; status = "disabled"; }; mdio: mdio@22004 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x22004 0x4>; clocks = <&cnm_clock>; }; i2c0: i2c@11000 { compatible = "marvell,mv78230-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; clocks = <&cnm_clock>; clock-names = "core"; interrupts = ; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c0_pins>; pinctrl-1 = <&i2c0_gpio>; scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; i2c1: i2c@11100 { compatible = "marvell,mv78230-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; clocks = <&cnm_clock>; clock-names = "core"; interrupts = ; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c1_pins>; pinctrl-1 = <&i2c1_gpio>; scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl0 0 0 32>; marvell,pwm-offset = <0x1f0>; interrupt-controller; #interrupt-cells = <2>; interrupts = , , , ; }; gpio1: gpio@18140 { reg = <0x18140 0x40>; compatible = "marvell,orion-gpio"; ngpios = <14>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl0 0 32 14>; marvell,pwm-offset = <0x1f0>; interrupt-controller; #interrupt-cells = <2>; interrupts = , ; }; }; mmc_dma: bus@80500000 { compatible = "simple-bus"; ranges; #address-cells = <0x2>; #size-cells = <0x2>; reg = <0x0 0x80500000 0x0 0x100000>; dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>; dma-coherent; sdhci: mmc@805c0000 { compatible = "marvell,ac5-sdhci", "marvell,armada-ap806-sdhci"; reg = <0x0 0x805c0000 0x0 0x1000>; interrupts = ; clocks = <&emmc_clock>, <&cnm_clock>; clock-names = "core", "axi"; bus-width = <8>; non-removable; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; }; }; /* * Dedicated section for devices behind 32bit controllers so we * can configure specific DMA mapping for them */ behind-32bit-controller@7f000000 { compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; /* Host phy ram starts at 0x200M */ dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; dma-coherent; eth0: ethernet@20000 { compatible = "marvell,armada-ac5-neta"; reg = <0x0 0x20000 0x0 0x4000>; interrupts = ; clocks = <&cnm_clock>; phy-mode = "sgmii"; status = "disabled"; }; eth1: ethernet@24000 { compatible = "marvell,armada-ac5-neta"; reg = <0x0 0x24000 0x0 0x4000>; interrupts = ; clocks = <&cnm_clock>; phy-mode = "sgmii"; status = "disabled"; }; usb0: usb@80000 { compatible = "marvell,orion-ehci"; reg = <0x0 0x80000 0x0 0x500>; interrupts = ; status = "disabled"; }; usb1: usb@a0000 { compatible = "marvell,orion-ehci"; reg = <0x0 0xa0000 0x0 0x500>; interrupts = ; status = "disabled"; }; }; pinctrl0: pinctrl@80020100 { compatible = "marvell,ac5-pinctrl"; reg = <0 0x80020100 0 0x20>; i2c0_pins: i2c0-pins { marvell,pins = "mpp26", "mpp27"; marvell,function = "i2c0"; }; i2c0_gpio: i2c0-gpio-pins { marvell,pins = "mpp26", "mpp27"; marvell,function = "gpio"; }; i2c1_pins: i2c1-pins { marvell,pins = "mpp20", "mpp21"; marvell,function = "i2c1"; }; i2c1_gpio: i2c1-gpio-pins { marvell,pins = "mpp20", "mpp21"; marvell,function = "i2c1"; }; }; spi0: spi@805a0000 { compatible = "marvell,armada-3700-spi"; reg = <0x0 0x805a0000 0x0 0x50>; #address-cells = <0x1>; #size-cells = <0x0>; clocks = <&spi_clock>; interrupts = ; num-cs = <1>; status = "disabled"; }; spi1: spi@805a8000 { compatible = "marvell,armada-3700-spi"; reg = <0x0 0x805a8000 0x0 0x50>; #address-cells = <0x1>; #size-cells = <0x0>; clocks = <&spi_clock>; interrupts = ; num-cs = <1>; status = "disabled"; }; nand: nand-controller@805b0000 { compatible = "marvell,ac5-nand-controller"; reg = <0x0 0x805b0000 0x0 0x00000054>; #address-cells = <0x1>; #size-cells = <0x0>; interrupts = ; clocks = <&nand_clock>; status = "disabled"; }; gic: interrupt-controller@80600000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ <0x0 0x80660000 0x0 0x40000>; /* GICR */ interrupts = ; }; }; clocks { cnm_clock: cnm-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <328000000>; }; spi_clock: spi-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; nand_clock: nand-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <400000000>; }; emmc_clock: emmc-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <400000000>; }; }; };